1. Field of the Invention
The present invention is directed to reset of a processor and, in particular, to multiple processors or controllers configured to ensure that an originating reset invoked in any one of the processors automatically triggers a forced reset in the remaining processors while maintaining the system state of the processors prior to the originating reset.
2. Description of Related Art
An electronic component such as a processor or controller may be reset for different reasons. For instance, the processor or controller may be reset initially upon activation. Processors or controllers are also subject to potential malfunction or defect, for example, due to a programming error in the software. A watchdog timer or some other type of error detection circuit is conventionally used as a safety device to confirm that the processor or controller is properly executing the software. The watchdog circuit which may be either external to or built into a processor resets the software when it determines that the system is not operating properly due to an electrical or programming error.
Software error detecting circuits such as watchdog circuits or timers are widely used. By way of example, U.S. Pat. No. 6,694,191 discloses an implanted medical device and handheld communication device in which the implantable medical device is capable of operating under control of different software programs. The medical device includes a main processor and a monitor processor. Each processor has an associated error detecting circuit. An error condition detected in one processor results in the resetting of that processor as well as triggering of an error condition in the other processor that will cause it to reset. When one of the processors is reset due to detection of an error, the other processor will sooner or later unless tripped by a different error first, detect an error related to an inter-processor communication failure that will cause it to reset as well.
Another resetting system is described in U.S. Pat. No. 4,803,682 wherein the system employs a main CPU and slave CPUs. In the patented resetting system, a breakdown detection circuit (watchdog timer) is provided only with the main microcomputer. The main CPU is designed to detect an error in the slave CPUs through communication therewith thereby eliminating the need for error detection in connection with each of the slave CPUs. In response to the detection of an error the main CPU introduces a reset signal to the slave CPUs. The main CPU generates strobe signals at a predetermined cycle. A watchdog timer connected to the main CPU outputs an error signal that resets the main CPU when the strobe signals are not generated. A control means introduces a reset signal into the slave CPUs on the basis of the generation of the error signal.
The patented systems discussed above are all limited to resetting of the processor based on the detection of an error thereby failing to recognize the need for resetting of the multiple processors with other sources of reset. Furthermore, the prior art of record does not address the need to restore operation of the processors to their respective system states prior to reset and the need to ensure synchronization of system states among the processors to allow proper communication therebetween.
It is therefore desirable to develop a reset design configuration for systems employing multiple processors or controllers so that an originating reset with respect to any one of the processors or controllers automatically invokes forced resetting of all remaining processors or controllers while also refreshing the system states of the respective processors to that prior to the originating reset.